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- Re: Intel and AMD RDMA implementation
In article <f2mai7-jes....@ntp.tmsw.no>,
Yes, er, unobviously :-)
No, I meant what I said, but meant 'being written to the device'.
I strongly disagree, in a well-designed asynchronous interface, but
I strongly agree in a POSIX-like one!
Regards,
Nick Maclaren. - Re: Intel and AMD RDMA implementation
That is so obvious that it shouldn't even need to be written down.
Unfortunately "obvious" is obviously a very non-obvious term, or
something like that.
So you meant to write 'in the process of being read'?
Right. Like, if the OS knows that it has exclusive access to a buffer,
it can employ all sorts of dirty tricks with safety, up to and including - Re: Intel and AMD RDMA implementation
In article <f50456ph3g65flpulq3n1bin6pdli l7...@4ax.com>,
Eh? I was quoting the specification itself!
In all reasonable standards, explicit constraints supersede implicit
ones. And the explicit constraint on when and how a buffer may be
used is what I quoted.
That's irrelevant. What is at issue is what an implementation is - Re: Intel and AMD RDMA implementation
In article <e01ddfe6-280f-485d-87ae-5b8b9 c6f0...@l20g2000yqm.googlegrou ps.com>,
The case of reading a buffer that is in the process of being written
(i.e. two read-only actions) is debatable. I agree with you, but
there are arguments in the other direction.
Regards,
Nick Maclaren. - Re: Redbook on the new z196 mainframes.
Itanium's 128 byte cache line seems positively puny then :)
rick jones - Re: Intel and AMD RDMA implementation
Well, you know, some of us were proposing asynchronous I/O at the same
time as threading. (I wasn't on POSIX, but my boss was. Hi Johm if you
are out there!)
Unfortunately, I think it was HP that came along with an asynch proposal
that they had implemented on top of kernel threading. Which ruined their - Re: Redbook on the new z196 mainframes.
Jason, can you explain why GUPS is so update heavy?
Sure, a workload of random updates seesm important. But similarly a
workload of random reads also seems important.
I think that we need two randoom read components:
(1) independent random reads
(2) dependent random reads, e.g. pointer chasing:
choose a random hash table - Re: Intel and AMD RDMA implementation
I really thought it was the other way around. Asynch I/O appeared in
most Unix(-like) OSes before threads did and I thought the POSIX
timeline reflected that as well.
Live and learn.
Badly written, I agree. I could argue that this is a paraphrasing of
the spec and not the spec itself ... but I see your concern. - Re: Intel and AMD RDMA implementation
In my considered opinion. Any program, that expects to operate under
any reasonable definition of correctness, cannot be concurrently
accessing any buffer that has I/O scheduled to/from it.
Mitch - DRAM Devices and Systems: A JEDEC-Sponsored Educational Event
[link]
I'll be hosting a 2-day tutorial on DRAM Devices and Systems in San
Jose on Oct 6-7. We've set forth an ambitious agenda where I'll try
to do a brain dump of a few things I've learned in the past few
years. Please join us if you can. - Re: Intel and AMD RDMA implementation
In article <aih356to4nkpn2518a8r80not679f 5h...@4ax.com>,
We are agreed there. However, (a) asynchronous I/O was introduced
later than threading (seriously) and (b) that's no excuse for making
a pig's ear of it.
See the specification of aio_read: "For any system action that changes
the process memory space while an asynchronous I/O is outstanding to the - Re: Intel and AMD RDMA implementation
POSIX is a *process* level sequential execution model which was
defined without considering concurrent threads. POSIX threads were an
afterthought that had to be designed around the already existing IO
model.
Undoubtedly.
What I'm missing is what you believe "is defined when it isn't".
The POSIX API includes synchronization to prevent concurrent access to - Re: Intel and AMD RDMA implementation
In article <r5b356900nnc1ubjb74p68ff6kb3f m0...@4ax.com>,
However, thread execution isn't.
You have missed the point. They have specified that something is
defined, when it isn't, at a deeper level than POSIX. Reading
data while it is in the process of being changed is not a clever
idea, at best.
No. Deadlock, unswappable processes and so on. - Re: Intel and AMD RDMA implementation
It's a sequential model.
Preventing concurrent access isn't really possible unless the buffer
page is mapped out of the process during DMA. You can make an
argument about that either way - on one hand remapping the buffer
makes asynch IO safe; but OTOH, page granularity could be a problem to
a program that needs a lot of small buffers. Besides which the API - Re: Effects of Memory Latency and Bandwidth on Supercomputer,Application Performance
Mea culpa, or wishful thinking on my part. :-(
OK, that was really what I was asking about.
Terje